commit 7012873c90eac541a290733c29794ba4bd138e67 Author: chenyue Date: Wed Jun 17 09:38:19 2026 +0800 初版可以用，但是最后一个位解析有问题。 diff --git a/1-BISS/__init__.py b/1-BISS/__init__.py new file mode 100644 index 0000000..2a36b06 --- /dev/null +++ b/1-BISS/__init__.py @@ -0,0 +1,25 @@ +## +## This file is part of the libsigrokdecode project. +## +## Copyright (C) 2012 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +''' +I²C (Inter-Integrated Circuit) is a bidirectional, multi-master +bus using two signals (SCL = serial clock line, SDA = serial data line). +''' + +from .pd import Decoder diff --git a/1-BISS/__pycache__/__init__.cpython-36.pyc b/1-BISS/__pycache__/__init__.cpython-36.pyc new file mode 100644 index 0000000..e3407e9 Binary files /dev/null and b/1-BISS/__pycache__/__init__.cpython-36.pyc differ diff --git a/1-BISS/__pycache__/pd.cpython-36.pyc b/1-BISS/__pycache__/pd.cpython-36.pyc new file mode 100644 index 0000000..4e53c4d Binary files /dev/null and b/1-BISS/__pycache__/pd.cpython-36.pyc differ diff --git a/1-BISS/pd.py b/1-BISS/pd.py new file mode 100644 index 0000000..e82a0bb --- /dev/null +++ b/1-BISS/pd.py @@ -0,0 +1,234 @@ +## +## This file is part of the libsigrokdecode project. +## +## Copyright (C) 2010-2016 Uwe Hermann +## Copyright (C) 2019 DreamSourceLab +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +# BiSS-C decoder (default): MSB-first, sample on SCL rising edge. +# Frame: 25 data bits + 6 CRC (CRC-6, polynomial x^6 + x^1 + x^0 (0x43) commonly used in BiSS) + +import sigrokdecode as srd + +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +: + - 'START' (START condition) + - 'START REPEAT' (Repeated START condition) + - 'ADDRESS READ' (Slave address, read) + - 'ADDRESS WRITE' (Slave address, write) + - 'DATA READ' (Data, read) + - 'DATA WRITE' (Data, write) + - 'STOP' (STOP condition) + - 'ACK' (ACK bit) + - 'NACK' (NACK bit) + - 'BITS' (: list of data/address bits and their ss/es numbers) + + is the data or address byte associated with the 'ADDRESS*' and 'DATA*' +command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). +For example, a slave address field could be 0x51 (instead of 0xa2). +For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' is None. +''' + +# CMD: [annotation-type-index, long annotation, short annotation] +proto = { + 'START': [0, 'Start', 'S'], + 'DATA READ': [1, 'Start repeat', 'Sr'], + 'STOP': [2, 'Stop', 'P'], + 'DATA READ1': [3, 'ACK', 'A'], + 'DATA READ2': [4, 'NACK', 'N'], + 'BIT': [5, 'Bit', 'B'], + 'ERR': [6, 'Address read', 'AR'], + 'CRC': [7, 'Address write', 'AW'], + 'DATA READ': [8, 'Data read', 'DR'], + 'DATA WRITE': [9, 'Data write', 'DW'], +} + +class Decoder(srd.Decoder): + api_version = 3 + id = '1:biss' + name = '1:BiSS' + longname = 'BiSS-C Encoder/Decoder' + desc = 'BiSS-C position sensor serial protocol (default decoding)' + license = 'gplv2+' + inputs = ['logic'] + outputs = ['biss'] + tags = ['Embedded/industrial'] + channels = ( + {'id': 'scl', 'type': 8, 'name': 'SCL', 'desc': 'Clock', 'idn':'dec_1biss_chan_scl'}, + {'id': 'sda', 'type': 108, 'name': 'SDA', 'desc': 'Serial data line', 'idn':'dec_1i2c_chan_sda'}, + ) + annotations = ( + ('7', 'start', 'Start condition'), + ('6', 'repeat-start', 'Repeat start condition'), + ('1', 'stop', 'Stop condition'), + ('5', 'ack', 'ACK'), + ('0', 'nack', 'NACK'), + ('208', 'bit', 'Data/address bit'), + ('112', 'address-read', 'Address read'), + ('111', 'address-write', 'Address write'), + ('110', 'data-read', 'Data read'), + ('109', 'data-write', 'Data write'), + + ) + annotation_rows = ( + ('bits', 'Bits', (5,)), + ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), + ('warnings', 'Warnings', (10,)), + + ) + binary = ( + ('address-read', 'Address read'), + ('address-write', 'Address write'), + ('data-read', 'Data read'), + ('data-write', 'Data write'), + ) + + def __init__(self): + self.reset() + + def reset(self): + self.samplerate = None + self.ss = self.es = self.ss_byte = -1 + self.bitcount = 0 + self.databyte = 0 + self.state = 'FIND START' + self.pdu_start = None + self.pdu_bits = 0 + self.bits = [] + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) + self.out_binary = self.register(srd.OUTPUT_BINARY) + self.out_bitrate = self.register(srd.OUTPUT_META, + meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit')) + + def putx(self, data): + self.put(self.ss, self.es, self.out_ann, data) + + def putp(self, data): + self.put(self.ss, self.es, self.out_python, data) + + def putb(self, data): + self.put(self.ss, self.es, self.out_binary, data) + + def handle_start(self): + self.ss, self.es = self.samplenum, self.samplenum + self.pdu_start = self.samplenum + self.pdu_bits = 0 + cmd = 'START' + self.putp([cmd, None]) + self.putx([proto[cmd][0], proto[cmd][1:]]) + self.state = 'FIND DATA' + self.bitcount = self.databyte = 0 + self.bits = [] + + # Gather 8 bits of data plus the ACK/NACK bit. + def handle_data(self, scl, sda,cmd,size,next_state): + self.pdu_bits += 1 + + # Address and data are transmitted MSB-first. + self.databyte <<= 1 + self.databyte |= sda + + # Remember the start of the first data/address bit. + if self.bitcount == 0: + self.ss_byte = self.samplenum + + # Store individual bits and their start/end samplenumbers. + # In the list, index 0 represents the LSB (I2C transmits MSB-first). + self.bits.insert(0, [sda, self.samplenum, self.samplenum]) + if self.bitcount > 0: + self.bits[1][2] = self.samplenum + if self.bitcount == (size - 1): + self.bitwidth = self.bits[0][2] - self.bits[1][2] + self.bits[0][2] += self.bitwidth + + # Return if we haven't collected all 8 + 1 bits, yet. + if self.bitcount < size: + self.bitcount += 1 + return + + d = self.databyte + bin_class = -1 + + self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth + + self.putp(['BITS', self.bits]) + self.putp([cmd, d]) + + self.putb([bin_class, d]) + + for bit in self.bits: + self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]]) + + + self.putx([proto[cmd][0], ['%s: {$}' % proto[cmd][1], '%s: {$}' % proto[cmd][2], '{$}', d]]) + + # Done with this packet. + self.bitcount = self.databyte = 0 + self.bits = [] + self.state = next_state + + + def handle_stop(self): + # Meta bitrate + if self.samplerate: + elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) + bitrate = int(1 / elapsed * self.pdu_bits) + self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate) + + cmd = 'STOP' + self.ss, self.es = self.samplenum, self.samplenum + self.putp([cmd, None]) + self.putx([proto[cmd][0], proto[cmd][1:]]) + self.state = 'FIND START' + self.bits = [] + + def decode(self): + while True: + # State machine. + if self.state == 'FIND START': + self.wait({0: 'h', 1: 'f'}) + self.handle_start() + elif self.state == 'FIND DATA': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ',2,'FIND DATA1') + elif self.state == 'FIND DATA1': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ1',6,'FIND DATA2') + elif self.state == 'FIND DATA2': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ2',13,'FIND ERR') + elif self.state == 'FIND ERR': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'ERR',2,'FIND CRC') + elif self.state == 'FIND CRC': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'CRC',6,'FIND STOP') + elif self.state == 'FIND STOP': + (scl, sda) = self.wait([{0: 'h', 1: 'r'}]) + self.handle_stop() +