From 7012873c90eac541a290733c29794ba4bd138e67 Mon Sep 17 00:00:00 2001 From: chenyue Date: Wed, 17 Jun 2026 09:38:19 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E7=89=88=E5=8F=AF=E4=BB=A5=E7=94=A8?= =?UTF-8?q?=EF=BC=8C=E4=BD=86=E6=98=AF=E6=9C=80=E5=90=8E=E4=B8=80=E4=B8=AA?= =?UTF-8?q?=E4=BD=8D=E8=A7=A3=E6=9E=90=E6=9C=89=E9=97=AE=E9=A2=98=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- 1-BISS/__init__.py | 25 +++ 1-BISS/__pycache__/__init__.cpython-36.pyc | Bin 0 -> 326 bytes 1-BISS/__pycache__/pd.cpython-36.pyc | Bin 0 -> 6783 bytes 1-BISS/pd.py | 234 +++++++++++++++++++++ 4 files changed, 259 insertions(+) create mode 100644 1-BISS/__init__.py create mode 100644 1-BISS/__pycache__/__init__.cpython-36.pyc create mode 100644 1-BISS/__pycache__/pd.cpython-36.pyc create mode 100644 1-BISS/pd.py diff --git a/1-BISS/__init__.py b/1-BISS/__init__.py new file mode 100644 index 0000000..2a36b06 --- /dev/null +++ b/1-BISS/__init__.py @@ -0,0 +1,25 @@ +## +## This file is part of the libsigrokdecode project. +## +## Copyright (C) 2012 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +''' +I²C (Inter-Integrated Circuit) is a bidirectional, multi-master +bus using two signals (SCL = serial clock line, SDA = serial data line). +''' + +from .pd import Decoder diff --git a/1-BISS/__pycache__/__init__.cpython-36.pyc b/1-BISS/__pycache__/__init__.cpython-36.pyc new file mode 100644 index 0000000000000000000000000000000000000000..e3407e914ff283597e4fa367962ea8c023525435 GIT binary patch literal 326 zcmYjM!AiqG5Zxq|N}xBv>l_8J S9beX3v`Su|dKueG4#FQ16J1yU literal 0 HcmV?d00001 diff --git a/1-BISS/__pycache__/pd.cpython-36.pyc b/1-BISS/__pycache__/pd.cpython-36.pyc new file mode 100644 index 0000000000000000000000000000000000000000..4e53c4de3c0db41e95033449eac1258e58eb5ab1 GIT binary patch literal 6783 zcmb_gOLH5?5#HGcumHg~MUj%Mz_Oe&9ElR;*s>MJ79>)(ED54X%CunF>m_ChfdT<& zb}33QSgDHaROMAsxf184yr0U!hx~+`QaR@|ha8ezm|Swmi8&-+&nzBfq*N*upth%{ zr)RdOd-^f^On-m+Z?}%|Cyp4#pNyVg2KZ?_VFbVp&ZEFN z^FE$I+s_C1Ale~5%tz3U@-e;#?Kt1dC(usveSAOK1NJ7=}wk+yd z`Lh=!%Wv6gsGxdCL6r(teC|N-=hpyBC~z{dvhbsTXU|qdX}uCPpIF?eAKj>k;7E3Dy&6@HuK6KYk7UC@RQzgoc|DwJ zCd!TKtrMS;PPJaHl%$2#o1?R9%K_&BKUS&n^)MoCX@#Y#*n{^#eVk!FQUJG#>dq+RpZ0C^D7Yj_PSa(}C;SDeW=hvF4E zow0{5$bC8B>jUep)Ww<~H4n~I!ba7r)WBztZ&Y4xcY!BnKv_rV*_5e9+@4&Ot@=G_Adq{SiRD~X$ZfTu3{=Br7E7A54Ioh%I z{y>q|^z@1COiVdSF1)?dp}{b{-QQ+VKDxcjx509JJ4HIz3-q|SHGTYr?X()wQ+r+A zo<4s3xO6vsQLEI-;r8BF*Vp`-TEkzi2HEz2v>|CIZA6_=3}Q#yDU#dtvh9$5-E#*)RK0U;%IVav*Jz6%UMb=Y266!NJqKzE+M767DPU6|2^=BbovaI?y+in zc!yOfkt*TN0im-Nu~qXfgJ`gr>e;FXTdH0{^^$SVjZ&O(bH(D;S7|$GwH>=qOu|XX zRLw&%l3fw?wXBXe&~`Seql3r+oK7;ymg|$Q2+9?T?4ks5WdG$Wi*r{Ny}7H4uU;<5 zbbUSY8h4`Wh*ar#C|@YZB+>m^t;2ujd?7!7Rr4=bYQDH5`(pk}vx|AeY@C!nnuXVs zn2#{~6omL3o{(JBU<2y!vaYe!p(-i&0Ry!ieeOetw1fxRT!nU4troj$cRksbR%1O9 zSHUQX1l9m@rna+9hTLso8~nGw0Is&jX4mf7Snizi9ai}g*kh}}TsX0G(#bZ2qgVyB(Q~*77oFl( z&E)nb*)P#T$y|nKFq)r?+!mWeDLrY#7##Tnb28>okq@4s;$j+W_Qeq~0X(B3U%&E{ zWTBfXc2=2U5|TDEDj3Gaq>h9GGNmJ7ZGElBW0Py2*&{o1V2}WzyWp$ZAJyc=2-hE_D<@=L8`f_ z>QkZSw=hY|u%UF$PQnbH?lI0TP!H zhB$3e)0{9P8OeH)Oa?>3q#px|sgp!?xJ4Y3#sqpEg*BL-D2}1VlP3|vJM#_kJ0%+m zb0xQm-k8HSDOkGPxnbU8!X*l4rw#EJZsGvZp-O?4<_WBvjCpX_UN$x@zJHVU)1Es8 z90y17OmTM;vToWn-or7cIB-1ira7JhhY5}|iX*M4qGt`k`@oR_N4AIK!=5!hg^RL#+ha z0T6mdf0z$)qCwB&Mw#XyDBfc?|GZ?hoYfINe3#ub#Vv4>EDw_>h4G7ggf2K`tLEy< zP1)Kc`;FpUBs;RH9Vtg|?`1R^YdNq3S$QJHA>DYl2Px5;#Exve4mUdm4pYwS@O{t> z${Cbo2YQMZUF}hgx65;%0!chg^j$Z@o!7>ca(B8R;x0;8Ms-ir*QM?qvS{PNxu7c0 zruigp195zi&XT_4E(yt&q&=@L!t-3R`DXIT@KpA_!<$WufUCpG*$X&jt-TREUK-y-;#P5l8oq zaHE1XC_0Hd06ACJTnCBpB(X6rQ^?z1sp^NJXcGN1ioUTsM2*MMCcYSWb>UIs{2sVN zk`GDSLfW>{%(W*_4GrNr$R^MqV77_iWsZU7nl_tYHUimhXqyw}5F0SZ%nX~tGrg()-zSD{_V1()WgKPdoW09J+9tco zf@C>B8CJUSN30iDOcPKpvV_$fY%40}>15{}n)x`^44j)qly!}}Y(MEq1^Nl3i@nB} zvB@GEK~;}9W8m4OaSAmQ00?(mDySedQurW>se%B)u!nrS+P6cenW$gs6nc%ZojOGj z@dnflW>97JAr%CMcW9Z)J(bIQFEHA@MpOYWot0|ckF?5Fw!TSIRLWNMm-073wEt)e zo!`6pTbo8EgR0*M171wVCGA5^)YnPQ^~PWEs&E3pfFB%0QXhvGjF7ohLdWSIZ5yp; zR>yD_Cer0rWps|Cb&uV?2GznyIKWQJ00CIieBf`H);9CT~P2f8OzDwXf0ZMV=`viVK;D-PY zm?{b&C8cd~iNKGDp6VVDZDuOPcYl@IL$tlbZixcnmkIoY2u!@L=}N{qqW=saXNeyZ z{!;=!2Y6uiXu|AKg4wfwv%7WVm0!@@UlMpg;8y^-$LRAEePZ=InfAQ3I$y^v#FH7% zySeUHkUQSol!!xqX9k)_Fp0Hj;3*UH2ae*&#mN&(6jDq?VL#Wy2d`xRnGemRsb zec-JH)lhsuv-{AgN4_d)+*cGDf2cQ!Z(!wqZk?vo8WHM25ST@QS1kiu`+ls0o+{kh*H{;rF5-t4) z+*vo}4ykwKY?%owWl_JOJw| +## Copyright (C) 2019 DreamSourceLab +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +# BiSS-C decoder (default): MSB-first, sample on SCL rising edge. +# Frame: 25 data bits + 6 CRC (CRC-6, polynomial x^6 + x^1 + x^0 (0x43) commonly used in BiSS) + +import sigrokdecode as srd + +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +: + - 'START' (START condition) + - 'START REPEAT' (Repeated START condition) + - 'ADDRESS READ' (Slave address, read) + - 'ADDRESS WRITE' (Slave address, write) + - 'DATA READ' (Data, read) + - 'DATA WRITE' (Data, write) + - 'STOP' (STOP condition) + - 'ACK' (ACK bit) + - 'NACK' (NACK bit) + - 'BITS' (: list of data/address bits and their ss/es numbers) + + is the data or address byte associated with the 'ADDRESS*' and 'DATA*' +command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). +For example, a slave address field could be 0x51 (instead of 0xa2). +For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' is None. +''' + +# CMD: [annotation-type-index, long annotation, short annotation] +proto = { + 'START': [0, 'Start', 'S'], + 'DATA READ': [1, 'Start repeat', 'Sr'], + 'STOP': [2, 'Stop', 'P'], + 'DATA READ1': [3, 'ACK', 'A'], + 'DATA READ2': [4, 'NACK', 'N'], + 'BIT': [5, 'Bit', 'B'], + 'ERR': [6, 'Address read', 'AR'], + 'CRC': [7, 'Address write', 'AW'], + 'DATA READ': [8, 'Data read', 'DR'], + 'DATA WRITE': [9, 'Data write', 'DW'], +} + +class Decoder(srd.Decoder): + api_version = 3 + id = '1:biss' + name = '1:BiSS' + longname = 'BiSS-C Encoder/Decoder' + desc = 'BiSS-C position sensor serial protocol (default decoding)' + license = 'gplv2+' + inputs = ['logic'] + outputs = ['biss'] + tags = ['Embedded/industrial'] + channels = ( + {'id': 'scl', 'type': 8, 'name': 'SCL', 'desc': 'Clock', 'idn':'dec_1biss_chan_scl'}, + {'id': 'sda', 'type': 108, 'name': 'SDA', 'desc': 'Serial data line', 'idn':'dec_1i2c_chan_sda'}, + ) + annotations = ( + ('7', 'start', 'Start condition'), + ('6', 'repeat-start', 'Repeat start condition'), + ('1', 'stop', 'Stop condition'), + ('5', 'ack', 'ACK'), + ('0', 'nack', 'NACK'), + ('208', 'bit', 'Data/address bit'), + ('112', 'address-read', 'Address read'), + ('111', 'address-write', 'Address write'), + ('110', 'data-read', 'Data read'), + ('109', 'data-write', 'Data write'), + + ) + annotation_rows = ( + ('bits', 'Bits', (5,)), + ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), + ('warnings', 'Warnings', (10,)), + + ) + binary = ( + ('address-read', 'Address read'), + ('address-write', 'Address write'), + ('data-read', 'Data read'), + ('data-write', 'Data write'), + ) + + def __init__(self): + self.reset() + + def reset(self): + self.samplerate = None + self.ss = self.es = self.ss_byte = -1 + self.bitcount = 0 + self.databyte = 0 + self.state = 'FIND START' + self.pdu_start = None + self.pdu_bits = 0 + self.bits = [] + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) + self.out_binary = self.register(srd.OUTPUT_BINARY) + self.out_bitrate = self.register(srd.OUTPUT_META, + meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit')) + + def putx(self, data): + self.put(self.ss, self.es, self.out_ann, data) + + def putp(self, data): + self.put(self.ss, self.es, self.out_python, data) + + def putb(self, data): + self.put(self.ss, self.es, self.out_binary, data) + + def handle_start(self): + self.ss, self.es = self.samplenum, self.samplenum + self.pdu_start = self.samplenum + self.pdu_bits = 0 + cmd = 'START' + self.putp([cmd, None]) + self.putx([proto[cmd][0], proto[cmd][1:]]) + self.state = 'FIND DATA' + self.bitcount = self.databyte = 0 + self.bits = [] + + # Gather 8 bits of data plus the ACK/NACK bit. + def handle_data(self, scl, sda,cmd,size,next_state): + self.pdu_bits += 1 + + # Address and data are transmitted MSB-first. + self.databyte <<= 1 + self.databyte |= sda + + # Remember the start of the first data/address bit. + if self.bitcount == 0: + self.ss_byte = self.samplenum + + # Store individual bits and their start/end samplenumbers. + # In the list, index 0 represents the LSB (I2C transmits MSB-first). + self.bits.insert(0, [sda, self.samplenum, self.samplenum]) + if self.bitcount > 0: + self.bits[1][2] = self.samplenum + if self.bitcount == (size - 1): + self.bitwidth = self.bits[0][2] - self.bits[1][2] + self.bits[0][2] += self.bitwidth + + # Return if we haven't collected all 8 + 1 bits, yet. + if self.bitcount < size: + self.bitcount += 1 + return + + d = self.databyte + bin_class = -1 + + self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth + + self.putp(['BITS', self.bits]) + self.putp([cmd, d]) + + self.putb([bin_class, d]) + + for bit in self.bits: + self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]]) + + + self.putx([proto[cmd][0], ['%s: {$}' % proto[cmd][1], '%s: {$}' % proto[cmd][2], '{$}', d]]) + + # Done with this packet. + self.bitcount = self.databyte = 0 + self.bits = [] + self.state = next_state + + + def handle_stop(self): + # Meta bitrate + if self.samplerate: + elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) + bitrate = int(1 / elapsed * self.pdu_bits) + self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate) + + cmd = 'STOP' + self.ss, self.es = self.samplenum, self.samplenum + self.putp([cmd, None]) + self.putx([proto[cmd][0], proto[cmd][1:]]) + self.state = 'FIND START' + self.bits = [] + + def decode(self): + while True: + # State machine. + if self.state == 'FIND START': + self.wait({0: 'h', 1: 'f'}) + self.handle_start() + elif self.state == 'FIND DATA': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ',2,'FIND DATA1') + elif self.state == 'FIND DATA1': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ1',6,'FIND DATA2') + elif self.state == 'FIND DATA2': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'DATA READ2',13,'FIND ERR') + elif self.state == 'FIND ERR': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'ERR',2,'FIND CRC') + elif self.state == 'FIND CRC': + (scl, sda) = self.wait([{0: 'f'}]) + self.handle_data(scl, sda,'CRC',6,'FIND STOP') + elif self.state == 'FIND STOP': + (scl, sda) = self.wait([{0: 'h', 1: 'r'}]) + self.handle_stop() +